Intel Haswell-EP Platform Detailed

[siopao1984]

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A certain DRAM major's frantic lobbying for the arrival of DDR4 seems to be paying off, as we're seeing some of the first leaks of information related to Intel's next-generation enterprise platform, Haswell-EP, slated for 2013-2014. Three crucial slides related to the platform component arrangement, the innards of the processor and core-logic themselves, were leaked.The first and most important portion of a leaked slide reveals the arrangement of the various key components in the platform. It reveals an arrangement that is not much different from today's Sandy Bridge-EP platforms, in which n-number of CPU sockets are wired to each other using fast QuickPath Interconnect (QPI). Intel will use dual-channel QPI, which doubles bandwidth over what is available with today's enterprise platforms. Assuming each channel is clocked at 6.4 GT/s, the cumulative bandwidth would amount to 51.2 GB/s.

Each socket will have four DDR4 DRAM channels. The DDR4 DRAM specification will introduce a fundamental change in the topology of DRAM components, which will be arranged "point-to-point". Each DRAM "channel" from the memory controller will support just one DRAM module, but there will be greater scope for DRAM makers to scale up densities of the modules with advancements in technology and silicon fabrication process. Much like Sandy Bridge-EP, Haswell-EP will see a bulk of the platform's PCI-Express lane budget being care of the processors' system agents; and will require external chipset for peripheral connectivity.One significant and much-required change here is that the chipset will not hold the GbE interfaces for the platform. It is estimated that 1 GbE would reach obsoletion, at least in the enterprise space, in which faster interfaces such as 10 GbE, or even InfiniBand would have become "common". Since these are extremely bandwidth-hungry interfaces, Intel restructured the platform in a way that "common" onboard network interface controllers will be wired to the PCI-Express root complexes of the processors, rather than the chipset.(this article is spread across three pages)

Read more: Intel Haswell-EP Platform Detailed by VR-Zone.com

[siopao1984]

While the slides don't go into deep micro-architecture related details, it does give a fair idea of how things are arranged on the Haswell-EP die. The components on the chip are arranged much in the same way as they are, on Sandy Bridge-EP, only that the scale of things appear to have gone up. Oversimplified, the die consists of cores, their complementary slices of last-level cache (L3 cache), system agent, memory controller, PCI-Express root complex, and QPI root complex connected with a ring-bus. Components are enabled/disabled by controlling the "ring-stops" (points where the bus picks up or drops off data/instructions) for each of the components, to carve out the various SKUs based on the silicon.



As mentioned earlier, 22 nm will be Intel's silicon fabrication process of choice, which will have matured quite a bit, when Haswell-EP's stint at the market arrives. While the diagram above doesn't give a clear picture about the number of cores Intel wants to cram onto the silicon, it's likely that there are 14 cores. One can deduce that looking at the total L3 cache amount mentioned (up to 35 MB), and amount of cache complementary to each core (around 2560 KB). That works out to 14 cores. Even in today's processor architectures by Intel, the L3 cache isn't a monolithic slab of SRAM, even though it is shared between all the cores. It consists of sub-divisions, which can be toggled to alter the amount L3 cache the various processor models end up with.

The system agent performs most of the ancillary functions of the processor. The integrated memory controller (IMC) will support the new DDR4 DRAM specification, which enables greater speeds and higher densities at lower voltages. The Haswell-EP IMC supports quad-channel DDR4-2133 MHz. The PCI-Express root complex will be PCI-Express Gen 3.0 compliant, and will include 40 lanes on the Haswell-EP and 24 lanes on Haswell-EN.

While every Haswell-EP processor comes with DMI, with which it can talk to the chipset, not every socket will be wired to the chipset. The sockets will be wired to each other in a kind of mesh-topology, using QPI links, and one of the processors will be wired to the chipset over DMI (and DMI-assisting PCI-Express links, if any).

A few other features mentioned in the above slide include HyperThreading, per core P-state, uncore frequency scaling, a newer version of Turbo Boost, and an integrated VRM control logic, which is probably how Intel will mandate a new VRD specification without bothering about inconsistencies between the various motherboards with regards to VRM design, out in the market.

The new processors will come with massive TDPs, in the range of 130~160 Watts.

[siopao1984]

The next major component in the Haswell-EP platform is its chipset, codenamed "Wellsburg." It will be branded Intel C610 series platform hub. Intel will take advantage of a newer silicon fabrication process (32 nm sounds likely), to cram more components on the chipset's silicon, without making it larger. To that effect, Intel mentioned the package size of the C610 doesn't exceed 25 x 25 mm, and its TDP (at maximum load) doesn't exceed 7W.



The chipset integrates a clock generator, it can share this clock with other components on the platform, or even be configured to rely on external clock signal. In terms of storage connectivity, we see a greater proliferation of new generation interfaces, such as SATA revision 3.0 and USB 3.0 SuperSpeed. The chipset can drive no less than ten SATA 6 Gb/s ports, with enterprise Rapid Storage Technology (RSTe) RAID support, with optional SSD caching (similar to Smart Response Technology). The C610 "Wellsburg" chipset will also feature a new USB port load-out, with six USB 3.0 and eight USB 2.0 ports. The reminiscent of today's GbE LAN PHYs are still there with the chipset, although it's unlikely that mainstram server boards will use it. Entry level ones will probably still use a couple of GbE controllers.

In conclusion, Haswell-EP looks like a monstrous concoction for enterprise platforms, with a focus on facilitating tomorrow's high bandwidth network interfaces.

The source of the slides is ChipHell.

[BrianBCBF]

lamia ani.. d lng guro q mag ups from sandy to ivy... il w8 for you haswell.. hmmm