Why the initial desktop Sandy Bridge-E chips has only six (of eight) cores enabled? by VR-Zone.com
We all know the Sandy Bridge E die has a total of 8 cores and 20 MB L3 cache, in addition to dual QPI links and quad DDR3 memory channels. Since the Xeon E5 workstation and server parts will have all of them, why are the desktop ones left with only six cores and 15 MB L3 cache? Look at the TDP (thermal design power) for an answer...
There was disappointment in some of the enthusiasts' circles that the initial round of desktop Socket 2011 Sandy Bridge E processors have one quarter of their cores and cache disabled. So, instead of 8 cores with 20 MB L3 cache, you get just 6 cores with 15 MB L3 enabled. The reasons mentioned, better to say speculated, along the way, were anything from the yields on this large die, or Intel's preference to sell full 8 core versions to the more lucrative workstation and server Xeon market, or even the fact that desktop apps or environments can still barely use even those 6 cores, not to mention a full set of eight.
There's another reason, that may top them all though - TDP. Yes, these are really big dies, with many cores and lots of cache - not as many as the Xeon E7 - Westmere-EX - series in the same 32 nm process, but E7's 10 cores and 30 MB cache top out at 2.4 GHz only. Here, we have an expectation that the full 8 core chip should still work at just above 3 GHz right at the announcement - at least in the '3-D workstations only' 150 W version. See the number? Now, well, desktops don't really go with more than 130 W TDP per socket these days, yet the per core clock has to be higher, to justify the migration from older Core i7, and to keep the difference with the LGA1155 4-core SB chips, as well as AMD Bulldozer.
So, to get 3.3 GHz or higher core speed, and fit it all into 130W TDP, a 6 core limit sounds about right for the current C series steppings at least. A future D stepping could enable higher clocks at the same TDP, or maybe enabling all the cores too at a similar speed. Intel's tradition for both Nehalem and Westmere was that, a quarter or two after the initial stepping, the next one would bring substantial improvements in frequency, or power, or both - usually one or two speed bumps within the same envelope. That was enough then, there's no reason to doubt it will be the same this time.
Else, we'd have to wait for the Ivy Bridge-E generation, still a year away...
Why the initial desktop Sandy Bridge-E chips has only six (of eight) cores enabled?
hehehehe
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